1) Field of the Invention
The invention herein relates to a method for increasing the transmit and receive efficiency of an embedded Ethernet controller transmit and receive efficiency.
2) Description of the Prior Art
Due to the prolific growth of the computer information industry in recent years, a variety of electronic products and peripheral equipment have been continuously developed and, furthermore, widely utilized in life and work environments. Such development trends have not only quickened information dispersal speed and efficiency, but have greatly benefited human life and work. To meet user demand, firms that design and manufacture such said electronic products are producing convenient, portable, and easy-to-use electronic products, each based on lightweight and ultra-compact design concepts and the availability of a wide range of different function expansion components that can be plugged into the said electronics, thereby providing for the flexible application of electronic products developed.
The devices commonly being utilized at present in small home or personal offices (SOHO) for connecting to a plurality of personal computers and wide bandwidth networks are called as residential gateways or SOHO routers (both of them are referred as gateway in this invention). Referring to FIG. 1, the internal key components of the said gateway(s) include a central processing unit 2 and one to three Ethernet media access controllers 3 (Ethernet MAC). Conventionally, the said controllers 3 are independently and individually mounted on a circuit board, but they are now integrated into an ASIC chip as an embedded Ethernet MAC controllers (E_MAC) along with other components and installed into the said gateway(s), which not only effectively reducing the physical size of embedded Ethernet MAC controllers, but also enabling the transmission and reception of Ethernet packets. Generally speaking, since the operating principles of the said embedded Ethernet MAC controller 1 involves the utilization of a bus master direct memory access (M_DMA) controller circuit 4 that enables each said Ethernet MAC to access data via the bus master and thus directly access data in memory 5 without going through the central processing unit 2, the task load of the central processing unit 2 is thereby lessened to increase the operating efficiency of the said embedded Ethernet MAC controller 1.
Generally, there are two main types of management for the embedded Ethernet MAC controller 1 to utilize the buffers and memories installed thereon. The first type accesses the following Ethernet packet information discretely stored in different receive or transmit buffers mapped in the memory 5 (such as synchronous dynamic RAM or SDRAM):    (1) Packet descriptor: Including packet length, status, and allocation address, etc.,    (2) Packet header: Including destination address (DA), source address (SA) and type (TYPE),    (3) Packet data, and    (4) Packet CRC.For example, a US company namely Intel Corp. utilizes this type in designing the said Ethernet controller(s). Another type places the packet descriptor and packet data together in a same receive or transmit buffer, for example, a Taiwanese company namely Realtek Semiconductor Co. utilizes such a type in designing the said Ethernet controller(s). In the method of the said first type, the buffer memory allocation of the said Ethernet controller(s) is more flexible, however since the operation of the master bus direct memory access (M_DMA Cycle) must be tasked twice, this squanders one instance of bus arbitration time. In the method of the second type, since the said Ethernet controller(s) are incapable of executing space allocation of the buffer dynamic memory, the space allocation of the buffer memory is relatively inflexible, though only a single instance of bus arbitration time is required.
The controller designed in the invention is mainly based on the method of the said second type, and is improved and embedded in a single chip to effectively raise the allocation flexibility of its buffer memory space and thereby increase its overall efficiency. As for the method of the said first type, since the present invention has no intention to improve the controller therefor, the method of the said first type will not be further elaborated in the following description of the invention.
In the said embedded Ethernet MAC controller designed by the said method of the second type, the packet processing can be divided into two sections, i.e. transmit module Tx and receive module Rx, depending on the way of processing the packets. Generally, the said Tx needs approximately four to eight fixed-size transmit buffers (respectively labeled Tx-Buffer #0 . . . Tx-Buffer #n, wherein n=0, 1, 2, 3, . . . ), as indicated in FIG. 2, that are utilized for temporarily storing the transmit packets, each Tx-Buffer using two registers, XSTATUS and XADDR, to map and manage the buffer areas. Within the said registers, XSTATUS is utilized to report the transmit status as well as define some of the specific transmit setting and the transmit packet length, while XADDR is utilized to set the starting address (transmit packet's address for Tx descriptor) of a transmit packet in the transmit buffer (Tx-Buffer), the transmit operating principle thereof is described as follows:
First, the central processing unit (CPU) writes the transmit packet into the successive positions within SDRAM sequentially, wherein the starting position being written is corresponding to the value in XADDR register, and when the CPU issues a transmit trigger command with respect to a Tx enable bit in the XSTATUS register, it activates the function of the master bus direct memory access (M_DMA) of the transmit module Tx to read the packet from the starting position corresponding to the XADDR register in the SDRAM after obtaining the control right to access the master bus, and to write the transmit packet into the internal transmit first-in first-out (FIFO) data queue of the said embedded Ethernet MAC controller 1 for transmitting. The status after transmission will then be written back into the status bit in XSTATUS register.
With respect to the receive module Rx, it needs approximately two to four adjustable receive buffers (respectively labeled Rx-Buffer #0 . . . Rx-Buffer #n, wherein n=0, 1, 2, 3, . . . ), as indicated in FIG. 3, that are utilized for temporarily storing the receive packets each including the following items:
(1) A Rx packet descriptor that occupies four bytes of memory space;
(2) Packet header: Including the destination address (Rx-DA) and the source address (Rx-SA), each occupying six bytes of memory space; and type (Rx-TYPE), occupying two bytes of memory space;
(3) Packet data; and
(4) A packet CRC that occupies four bytes of memory space.
Each Rx-Buffer utilizes three registers, RSTATUS, RADR, and RDHA-PTR, to map and manage the buffer areas. Within each said register, RSTATUS is utilized to report the receive status as well as define some of the specific receive setting, specify the Rx buffer size, and determine whether the M_DMA operation is capable of writing an incoming packet into this buffer. RADR is utilized to report the starting address of the Rx-Buffer, while RDHA-PTR is utilized to store the current pointer of the M_DMA operation in the receive module. The receive operating principles thereof is described as follows:
When the Rx_FIFO receives a packet that is larger in size than a certain threshold value, it activates the function of M_DMA of the receive module Rx and writes the receive packet into the Rx-Buffer after obtaining the control right of accessing the master bus. After each of the receive packet is written, the status and length values thereof are written back into the beginning of the receive descriptor.
Additionally, the writing sequence involves therein is described as follows:
First, placing the packet at the address in the SDRAM designated by the RADR register and thereafter placing the packet being received at the address next to the previous packet until the Rx-Buffer is full (when the Rx-Buffer size is greater than that in the said RSTATUS), and then placing the next packet into another Rx-Buffer, at which time the preceding Rx-Buffer is released after the process finished.
When the domain ports of a local area network (LAN) transmit packet data through the gateways of the embedded Ethernet MAC controller based on the said design type to the domain ports of a wide-area network (WAN), it has to insert an additional protocol header 30 (such as PPPoE, NAT, and DHCP, etc.) into the Ethernet packet data originally stored in the Tx-Buffer, as indicated in FIG. 4, before the Tx port of the said WAN transmits it to an Internet Service Provider (ISP) end; or, when being utilized in a LAN to transmit to a different IP domain, since it is only necessary to change some of the values in the protocol header of the original Ethernet packet data in the Tx-Buffer and then revise its destination address, source address, and status, the procedure thereof is simpler.
This also means that, the packet data 20 (data in Rx) received from the said LAN, as indicated in FIG. 3, must be moved by the said gateways to the memory area 10, as indicated in FIG. 2, and, only after being added with the required protocol header 30, as indicated in FIG. 4, can be transmitted out through the said WAN. At this time, since the CPU 2 of the said embedded Ethernet MAC controller 1 is required to move the received packet data to another memory area as well as update and re-arrange for transmit buffer usage, this wastes lots of CPU processing performance. Furthermore, referring to the structure shown in FIG. 3, since each packet is consecutively placed in the Rx-Buffer during reception, when the Rx-Buffers serve as Tx-Buffers, no surplus space is available for the additional insertion of protocol headers.
Therefore, how to design a type of embedded Ethernet MAC controller capable of receiving packets sent from LAN, maintaining a major portion of the received packet data at the original storage position in their receive buffers, inserting an additional protocol header before transmitting the packets to a WAN, and thereby effectively preventing. CPU from meaningless time and performance consuming due to moving packet data should be the major target for solving and overcoming the problems in the conventional embedded Ethernet MAC controller.